Expand description
Driver for the Flow Controller of the Tegra X1.
See Chapter 17 in the Tegra X1 Technical Reference Manual for details.
Description
The Flow Controller provides the sequencing of hardware-controlled CPU power states for the main CPU complex and the BPMP.
Modules
Bitfields of the FLOW_CTLR_BPMP_CLUSTER_CONTROL_0 register.
Bitfields of the FLOW_CTLR_CC4_CORE_<x>_CTRL_0 register.
Bitfields of the FLOW_CTLR_CC4_FC_STATUS_0 register.
Bitfields of the FLOW_CTLR_CC4_HVC_CONTROL_0 register.
Bitfields of the FLOW_CTLR_CC4_HVC_RETRY_0 register.
Bitfields of the FLOW_CTLR_CC4_RETENTION_CONTROL_0 register.
Bitfields of the FLOW_CTLR_CLUSTER_CONTROL_0 register.
Bitfields of the FLOW_CTLR_COP_CSR_0 register.
Bitfields of the FLOW_CTLR_CORE_<x>_IDLE_COUNTER_0 register.
Bitfields of the FLOW_CTLR_CPU_<x>_CSR_0 register.
Bitfields of the FLOW_CTLR_CPU_PWR_CSR_0 register.
Bitfields of the FLOW_CTLR_FC_SEQUENCE_INTERCEPT_0 register.
Bitfields of the FLOW_CTLR_FLOW_CTLR_SPARE_0 register.
Bitfields of the FLOW_CTLR_FLOW_DBG_CNT0_0 register.
Bitfields of the FLOW_CTLR_FLOW_DBG_CNT1_0 register.
Bitfields of the FLOW_CTLR_FLOW_DBG_QUAL_0 register.
Bitfields of the FLOW_CTLR_FLOW_DBG_SEL_0 register.
Bitfields of the FLOW_CTLR_HALT_COP_EVENTS_0 register.
Bitfields of the FLOW_CTLR_HALT_CPU_<x>_EVENTS_0 register.
Bitfields of the FLOW_CTLR_L2FLUSH_CONTROL_0 register.
Bitfields of the FLOW_CTLR_L2FLUSH_TIMEOUT_CNTR_0 register.
Bitfields of the FLOW_CTLR_MPID_0 register.
Bitfields of the FLOW_CTLR_RAM_REPAIR_0 register.
Bitfields of the FLOW_CTLR_XRQ_EVENTS_0 register.
Structs
Constants
A pointer to the Flow register block that can be accessed by dereferencing it.
Functions
Powers off the BPMP processor.
Powers down the given CPU.
Disable routing legacy FIQ to the GICD.
Enable routing legacy FIQ to the GICD.
Informs the BPMP that the cluster power-up sequence has completed.
Powers on the BPMP processor.
Powers up the given CPU.