Expand description
Driver for Tegra X1 Multi-Purpose Pins and Pin Multiplexing.
See Chapter 9 in the Tegra X1 Technical Reference Manual for details.
Description
Tegra X1 devices can be configured with different I/O functions on particular pins to enable their operation in a variety of different configurations.
Many of the pins on Tegra X1 devices are connected to Multi-Purpose I/O (MPIO) pads.
An MPIO can operate in two modes: either acting as a signal for a particular I/O controller,
referred to as Special-Function I/O (SFIO) or as a software-controlled General-Purpose
I/O function, referred to as Gpio.
Though each MPIO has up to 5 functions (a GPIO function and up to 4 SFIO functions), a given MPIO can only act as a single function at a given point in time. The Pinmux controller in Tegra X1 devices includes the logic and registers to select a particular function for each MPIO.
Configuration
Various get_ and set_ methods are provided to configure PinGrPs (Pin Group Pads)
or to query their state. Many devices depend on proper Pin Multiplexing, so this module
provides the required functionality to drive the desired pins.
Safety
Many of the configuration methods on a PinGrP are actually considered unsafe because
wrong usage of them can cause permanent damage to the hardware which is at the user’s risk.
Modules
Pad Control Options for Pinmux registers.
Structs
Representation of the Pinmux registers.
Enums
State control for the Drive Type control bit as a part of pin configuration.
Pin Functions that can be loaded onto a pin to control its behavior.
Pin Groups on the Tegra X1 SoC that can be customized and variably configured.
State control for the I/O direction bit as a part of Pin configuration.
State control for the I/O High Voltage control bit as a part of pin configuration.
State control for the Lock bit as a part of Pin configuration.
State control for the Base Driver control bit as a part of pin configuration.
State control for the OD control bit as a part of pin configuration.
State control for the Parking bit as a part of Pin configuration.
State control for the Pull bit as a part of Pin configuration.
State control for the Schmitt Trigger control bit as a part of pin configuration.
State control for the Tristate bit as a part of Pin configuration.
Constants
Base address for Pinmux registers.
A pointer to the Pinmux register block that can be accessed by dereferencing it.