Expand description
Driver for the Tegra X1 Universal Asynchronous Receiver/Transmitter Controller.
See Chapter 36 in the Tegra X1 Technical Reference Manual for details.
Description
There are five UARTs available in total. The UARTs A through D, which are identical, are built into Tegra X1 devices and the fifth UART is located in the Audio Processing Engine.
These UARTs support both, 16450 and 16550 compatible modes, although this implementation specifically targets the 16550 mode.
Transmission speed
UART controllers support Clocks up to 200MHz with a baud rate of 12.5M.
The default supported and recommended baud rate is 115_200. If one wishes to
use a custom baud rate, they may have to alter the clock divisor configuration of
the corresponding UART device clock.
Initialization
Uarts need to be initialized with a given baud rate before they can be used.
use libtegra::uart::{Uart, BAUD_115200};
Uart::A.init(BAUD_115200);Communication
After a Uart was initialized, it can be used like this:
use core::fmt::Write;
use libtegra::uart::Uart;
writeln!(&mut Uart::A, "I got {} problems, but UART logging ain't one!", 99);Reading data is also supported:
use libtegra::uart::Uart;
let mut uart = Uart::A; // Less typing...
// Read a single byte.
let byte = uart.read_byte();
// Read 10 bytes into a buffer.
let mut buffer = [0; 10];
uart.read(&mut buffer);Flushing
In some cases, you may want to flush the underlying FIFOs:
use libtegra::uart::Uart;
Uart::A.flush();Modules
Bitfields of the UART_ASR_0 register.
Bitfields of the UART_IER_DLAB_0_0 register.
Bitfields of the UART_IIR_FCR_0 register.
Bitfields of the UART_IRDA_CSR_0 register.
Bitfields of the UART_LCR_0 register.
Bitfields of the UART_LSR_0 register.
Bitfields of the UART_MCR_0 register.
Bitfields of the UART_MIE_0 register.
Bitfields of the UART_MSR_0 register.
Bitfields of the UART_RX_FIFO_CFG_0 register.
Bitfields of the UART_SPR_0 register.
Bitfields of the UART_THR_DLAB_0_0 register.
Bitfields of the UART_VENDOR_STATUS_0_0 register.
Structs
Constants
The default baud rate that can be used to intiialize UARTs.
A pointer to the UART A register block that can be accessed by dereferencing it.
A pointer to the UART B register block that can be accessed by dereferencing it.
A pointer to the UART C register block that can be accessed by dereferencing it.
A pointer to the UART D register block that can be accessed by dereferencing it.
A pointer to the UART (AP)E register block that can be accessed by dereferencing it.